Wafer Level Packaging (WLP) is a technique for packaging and testing an entire wafer and then cutting the tested wafer into individual finished chips such that the finished chips after packaging are the same sizes as the dies. The WLP technology completely revolutionized traditional packaging technologies such as Ceramic Leadless Chip Carrier and Organic Leadless Chip Carrier. This technique meets the growing market demands for lighter, smaller, thinner, and lower-cost microelectronic products. Through the wafer-level chip-size packaging technique, the chip size may achieve a high-degree of miniaturization and, consequently, the chip cost is significantly reduced with the decrease of the chip size and the increase of the wafer size. The wafer-level chip-size packaging technique may enable a true integration of integrated circuit (IC) design, wafer fabrication, packaging and testing, and substrate manufacturing at the wafer level, representing one of current research focuses in the packaging technology and leading the future development trend.
Fan-out wafer level packaging is one type of wafer-level packaging technologies. For example, Chinese patent application 200910031885.0 disclosed one wafer-level fan-out chip packaging method, the process steps including: covering the circular carrier substrate surface with a stripping film and a thin film dielectric layer I sequentially, and forming photolithography pattern openings I on the thin film dielectric layer I; forming metal electrodes connecting the substrate and re-wiring metal wires on the photolithography pattern openings I and its surface; covering the surfaces of metal electrodes connecting the substrate, re-wiring metal wires, and thin film dielectric layer I with thin-film dielectric layer II, and forming photolithography pattern openings II on the thin film dielectric layer II; constructing metal electrodes connecting chips on the photolithography pattern openings II; flipping the chips onto the metal electrodes and performing plastic encapsulation and curing to form a packaging structure with a plastic sealant layer; separating the circular carrier substrate and the striping film from the packaging structure with the plastic sealant layer to form a plastic-encapsulated wafer; planting and reflowing balls to form solder balls or bumps; cutting the plastic-encapsulated wafer into individual finished fan-out chip structures.
However, the final products made by the above packaging method may only support a single chip function. To achieve complete system functions, peripheral circuits including capacitors, inductors or resistors may need to be added at the outside of the final products. Further, the above method may be unable to be applied to manufacturing of multi-layer packaging structures with complex connections. Further, when such packaging method is used, the system-level packaging integration degree may be still undesired.
The disclosed methods and systems are directed to solve one or more problems set forth above and other problems.